Field of the Disclosure
The present invention concerns integrated circuit fabrication and testing. More particularly, the present invention concerns a methodology and structure for testing multiple integrated circuit dies residing on a semiconductor wafer substrate.
Description of the Related Art
Conventional integrated circuit fabrication techniques normally involve the formation of several individual integrated circuit devices on a single semiconductor substrate, termed a wafer. After fabrication is completed the wafer is normally cut or scribed to separate the individual integrated circuit devices into individual devices, commonly called singulated devices or die, or into rows of devices, commonly called strips. Usually the individual singulated integrated circuit devices, “chips”, called dies or dice, are spaced apart from one another on the wafer to accommodate the cutting tool used to segment the wafer. The wafer thus has the appearance of a series of integrated circuit dies (dice) separated by intersecting lines that accommodate the cutting operation. These lines are commonly referred to as scribing lines, streets or lanes. Such dice can be placed into IC packaging and wires connected from the die to leads within the IC package. Testing can then be done on the package leads or contacts, which are relatively speaking much larger than the contact on the IC dies. The technology used for testing IC leaded packages therefore is not particularly analogous to wafer level testing and we have found principles from IC packed lead testing will not work without substantial modification and inventive input.
In many instances it is deemed advantageous to test the electrical functionality of the individual integrated circuit dies either at the wafer level or at the strip level. That is, before the wafer is segmented and the individual integrated circuit dies are separated from one another. Typically this testing is performed by placing a series of test probes in contact with electrical input and output (I/O) pads, or bonding pads or bumps that are formed on an exposed surface of each integrated circuit die. These I/O pads are usually connected to elements of a leadframe if the integrated circuit die is subsequently packaged. An example of such a tester is shown in U.S. Pat. No. 5,532,174 to Corrigan.
Semiconductor integrated circuit devices (“die”) can also be tested while they are still present on the semiconductor wafer on which they were formed. Such wafer level testing is traditionally accomplished on a per chip basis, in which probe tips are brought into contact with bond pads for a given chip using precision wafer handling system commonly called a wafer prober. For each application, a specifically designed spatial configuration of probes are matched to the spatial array of bonding pads in what is commonly called a probe array. In the wafer prober, either a single die or a plurality of die may be stimulated and tested through the probe tips via a tester. In the case where a single die is tested for each wafer prober index step, the probe array is commonly called single site. In the case where 2 or more die are tested for each wafer prober index step, the probe array is commonly called multi-site. After single or multisite die are tested, the wafer prober system indexes to the next die or set of die which are similarly tested, etc. The probe array are commonly fastened onto a Printed Circuit Board (PCB) element to enable routing of signal lines to connect with Test system; said assemble of probe array and PCB are commonly called a probe card.
However, wafer prober and large probe array systems also exist which are capable of testing an entire semiconductor wafer, either all dies (ie chips) on the wafer simultaneously or a significant fraction of the dies on the wafer simultaneously. Furthermore, such systems may also be used to test the die on the wafer beyond basic functionality to stress the chips for a limited period of time for the purpose of weeding out early latent failures, what is known in the art as “burn in”. An exemplary system is shown in U.S. Pat. No. 7,176,702 to Cram.